`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:32:57 11/05/2013 
// Design Name: 
// Module Name:    InterfaceCircuit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module InterfaceCircuit(
	 input clock,
	 input reset,
    input [7:0] data_in,
    input set_flag,
    input clr_flag,
    output [7:0] data_out,
    output rx_empty
    );

localparam STORE = 1'b0,
			  CLEAR = 1'b1;

reg next_state, current_state;	  
reg [7:0] buffer;
reg flagFF;

// Logica de Memoria
always @(negedge clock, negedge reset)
	if(~reset)
		current_state = STORE;
	else
		current_state = next_state;
		
// Logica de cambio de estado
always @*
	begin
		case (current_state)
			STORE:
				begin
					if(set_flag == 1)
						begin
							buffer = data_in;
							flagFF = 1'b1;
							next_state = CLEAR;
						end
					else
						next_state = STORE;
				end
			CLEAR:
				begin
					if(clr_flag == 1)
						begin
							flag_FF = 1'b0;
							next_state = STORE;
						end
					else
						next_state = CLEAR;
				end
		endcase
	end

//Logica de salida
always @*
	begin
		assign data_out = buffer;
		assign rx_empty = ~flagFF;
	end

endmodule
